Most computer systems made to this day are of the conventional von Neumann organization which has remained relatively unstructured with the objective of being "general purpose." However, over the past two decades, better understanding has been achieved in the exploitation of the potential of block-structured programming languages that represent complex algorithms. Block structuring of algorithms, i.e., nested declarations, is a natural form for the expression of such complex algorithms.
A particular computer system that was designed to employ block structuring of algorithms, or nested languages (and also nested data structures), is described in the Barton, et al., U.S. Pat. Nos. 3,461,434; 3,546,677 and 3,548,384. These patents describe a stack-oriented data processor where the stack mechanism, a first-in last-out mechanism, handles the flow of operators and associated parameters in a manner which reflects the nested structure of particular higher level languages that are designed to handle natural forms for the expression of complex algorithms. Such languages include ALGOL and ALGOL type languages, such as PL/1, C, and so forth, which are based on the block-structuring of algorithms, i.e., nested declarations. While this may appear to impose unnecessary constraints on system development, the resulting products, measured in terms of throughput and flexibility, suggest that design "constraints" may really have been design opportunities (Cf., E. I. Organick, Computer System Organization, Academic Press 1973).
A system of the type described in the above-identified Barton patents is oriented around the concept of a segmented memory and specially treated segments called stacks. The processor runs in an expression stack; operators take their arguments from the top of the stack and leave their results on the top of the stack. The data addressing space of the executing program (task) is mapped into the stack as well as other stacks linked to it and data items referenced by describers contained in the stack structure.
While the primary function of such computer systems is to perform data processing, such processing is accompanied by a variety of system operations. Through the cooperation of the various components within the computer system (including a central processing unit (CPU), a memory, and one or more I/O devices) a variety of system operations are performed. These system operations include memory to memory transfer, task scheduling and I/O request handling.
Memory to memory transfer relates to the movement of data between various memory locations. These transfers may be combined with data modification operations. In performing memory to memory transfers, a variety of operations are invoked. These include the buffering of addresses for storage and fetching, translation between logical and physical addresses, arbitration and control of memory requests, masking for byte level modification, and maintenance of parity to ensure error-free data transfer.
Task scheduling relates to the order in which various functions are performed by the computer system. Certain tasks are given predetermined intervals during which they must complete (also known as a time-slice). Other tasks are prioritized so that they may be completed before lower priority tasks are handled. Tasks may be initiated by user requests or by the operating system.
I/O request handling relates to the control necessary to ensure that requests are issued to the appropriate I/O devices, I/O operations are performed as desired, and I/O data which is returned as a result of an I/O operation is transmitted to the process which initiated the I/O request. In addition, various statistics are maintained concerning the progress and completion of I/O operations.
The performance of all of the operations described above places a major burden on the central processing unit. Although the basic objective of many computer systems is to perform data processing, the necessity for performing a variety of support functions to support data processing may significantly retard system response.
Prior art computer systems have sought to improve throughput through the use of a multiprocessor system. In such a system, several processors share data processing functions. By increasing the number of processors in a computer system, the prior art sought to develop a computer system which processed more data in a shorter period of time. Another approach taken by prior art computer systems was to use multiple dedicated processors, each programmed to perform a specific system operation.
While the prior art achieved an increase in system throughput, various disadvantages exist.
For example, while a plurality of processors have been introduced to computer systems to facilitate these operations, the failure of one processor in such a system may lead to a complete disruption of system operation.
Prior art systems suffered from a lack of modularity. Thus, unique system components needed to be designed specifically to perform predetermined functions.
Many prior art systems suffered from a severe lack of reliability. If one device failed within the system, system functions could not be transferred to another otherwise equivalent device within the system.
As the number of processors in a computer system has increased, more sophisticated error handling mechanisms have been required for efficient system operation. In addition, various processors have differing error handling needs. The prior art suffered from insufficient error handling capabilities for multiprocessor environments.
U.S. Pat. No. 4,454,575 issued to Bushaw et al. discloses a time-shared memory device which is controlled by a central processor unit. Although data processing is performed by peripheral devices, this reference discloses a system in which the peripheral devices are hardwired to perform unique I/O functions. There is no facility that allows expeditious data handling independent of the data processing task of the data processing system.
U.S. Pat. Nos. 4,228,496 and 4,356,550 to Katzman et al. disclose multiprocessor systems in which a plurality of processing modules can communicate with each other through a bus network. The multiprocessor system includes an input/output (I/O) system having multi-port device controllers and (I/O) buses connecting each device controller for access by the (I/O) channels in at least two different processor modules.